Programming languages

I’ve used a lot of programming languages, and besides that a few scripting languages.

Scripting is used to automate stuff, but probably use other tools under the hood. A programming language can probably do this by itself. Most of the time a programming language needs compiling into a executable form. Whereas a script is directly intepreted at runtime.

I’m not good at programming, but i understand the syntax and can read most of it.
My programming is mostly by example/copy-paste.
Below a list of programming languages and a table below that some scripting languages.

Sooo .. what do i like, still use and why?

Bash is my swiss army knife.
Making Web stuff? – PHP
Iot – C and Javascript
Advanced programming/Longer programs or Machine Learning – Python

And because of recent projects … i have to mention 6502 machinecode!

Programming languages i’ve used

BasicThe first programming language i learned. There are many dialects for many different systems.
PascalI learned to program in school.
Generic pascal and later Turbo Pascal
PLM/86This is relatively unknown programming language. Written for intel processors. It used a lot of ms-dos subroutines. Like dsso which stands for dos-standard-string-out.
dsso(@(‘Print this text’,eos));
And called a dos routine like below
(assembly example)
mov dx,(messageaddress)
mov ah,09h
int 21h
AssemblyStarted with 6502 assemby on my little home computer (a vic-20).
After that i learned to program 8085 assembly in school.
Also learned a little Z80 programming.
When i got a amiga i started with 68000 assembly.
And getting the hang of it, some friends and me started programming 80×86.
CFor a project I needed C programming to control a parallel port, for example for my controllable webcam.
Also recently the microcontrollers like the Arduino’s are programmed in C/C++
PerlPerl was also a interesting language, i bought myself a book and started with the examples.
One of my friends was a Perl wizard, but i could never get the hang of it. Even with his help.
Tcl/TKTCL stands for Tool Command Language, i used the TK extension. So Tcl/TK i used for creating GUI tools in linux. But like what i later used zenity and yad, i think these are more scripting languages.
PHPPHP i used extensively, one of my first big projects was a tunesearch engine with a mysql database.
PythonThe last years i’ve been using python more and more. Python has become the de facto standard for IT.
HaskellWell .. it is a programming language but i only use it to configure my Xmonad desktop.
JavascriptI’ve made a lot of webbased nonsence. PHP/CGI scripts/flash but i also used javascript.
Now i’m primarily using javascript for NodeRed

Scripting languages i’ve used

batDos batch files is a kind of scripting language
KshKorn Shell, i did a workshop ksh because i was a AIX admin.
Didn’t use this much, because you could install the linux toolkit, and could use bash after that.
BashI write a lot of things in bash, this is my preferred tool for fast and easy automation.
When it’s web based i use PHP
LuaI had to write some plugins for my Flightsim Setup

What about Sql, Dbase, Sed, Puredata and blocky those are all on the Programming Lanuages page of Wikipedia???
Well those i find more of a application markup language.
Then you can say abc-music and bmw (bagpipe music writer) are languages also!??

Some call Ansible a programming language, but this is incorrect. It is driven by python scripts and yaml config files.

Below some code part examples of different CPU assembly code

#6502 
    PUSH CX
    PUSH DI
    PUSH SI
    MOV AX,cry
    MOV BX,(2*40)
    MUL BX
    MOV DI,AX
    ADD DI,(2*31)
    MOV SI,adr1
    SUB SI,8       
    MOV CX,8

Z80
    LD H,00H
    LD B,01H
    LD A,(IX+00)
    OUT (01H),A
    LD A,(IY+00)
    OUT (02H),A
    DJNZ LUS3
    LD B,01H
    LD A,(IX+07)
    OUT (01H),A
    LD A,(IY+07)
    OUT (02H),A

#8085
    LDA 2050
    MOV H, A
    LDA 2051
    ADD H
    MOV L, A
    MVI A 00
    ADC A
    MOV H, A
    SHLD 3050
    HLT

#68000
    bsr send
    bsr delay2
    move.w #$38,d0
    bsr send
    bsr delay2
    move.w #$38,d0
    bsr send
    bsr delay2
    move.w #$01,d0
    bsr send
    bsr delay2
    move.w #$0c,d0
    bsr send
    move.w #$06,d0
    bsr send
    rts

#80x68
    mov bx,split
    and bx,1111111111b
    mov dx,3d4h
    mov al,18h
    mov ah,bl
    out dx,ax
    mov bl,bh
    xor bh,bh
    shl bx,1
    mov bx,[bx+offset ormsk]
    mov al,9
    out dx,al
    inc dx
    in al,dx
    and al,10111111b

For assembly i use or used below:
vasm – vasm is a portable and retargetable assembler – which can be used for a lot of different CPUs
masm – a assembler for 80×86, i used this for programming on DOS machines. Also for little projects i used the alway available debug executable.
seka/masterseka – programming 68000 on my amiga

6502 cont.

UPDATE: 20220823 Sid working

Kicad VIA/PIA tester

Above is my Kicad design (reverse engineering print below, which was made for my 6802CPU, which i could use to test the 6822 PIA)
The 6822 is simular to 6502 in design. So i’m going to redo this for my 6502.
The 7 segment displays are a start of hex-keyboard/display combo i’m going to post more of in the next days.

Below a part of the rom for the LCD dual line display.

Part of the ROM assembly code, top part is text (o.a. japanese)

Started to write routines which i can call to manipulate the display. Setting the pointer to a message, setting the line to use and a subset of controlls like: Center, Right, binary to ascii, scrolling, etcetera

        lda #0             ; set line number
        sta lineno         ; store
        jsr gotoline       ; goto line in display
        lda #<message      ; get address from message and store for printline subroutine
        sta messagestore
        lda #>message
        sta messagestore+1
        jsr printline      ; print

        lda #1  ; set line number
        sta lineno      ; store
        jsr gotoline
        lda #<message2
        sta messagestore
        lda #>message2
        sta messagestore+1
        jsr printline

Above additions:
New address decoder
Below left the new graphical display, below right a test board which shows address lines and decoded chip-enable lines.

A15 high -> ROM
A15 && A14 low -> RAM
combination of A15 low and A14 high – A13 and A12 wil select peripherals.

Adress decoding

Above is a start of a wirewrapped version, i also started a PCB design in KIcad that will continuously be changed as i alter designs.

UPDATE SID Working! Using new address decoder.

SID = $7000

makesound:
	lda #0
	sta SID+$5 ; Channel1 - attack/decay
	
	lda #250
	sta SID+$6 ; Channel1 - Sustain/Release
	
	lda #$95
	sta SID+$0 ; Channel1 - Frequency low-byte
	
	lda #$44
	sta SID+$1 ; Channel1 - Frequency high-byte

	lda #%00100001
	sta SID+$4 ; SAW + Gate

	lda #$0f
	sta SID+$18 ; Volume max

C64 Cartridge

Got IC Sockets in today, together with other goodies.

So i soldered the C64 Cartridge print.

Putting a bin on the eeprom

sudo minipro -p AT28C64 -w 8kcart.bin

Welll .. allmost working.
Some strange artifacts, but is running.

The long wire … is a ‘jumper’ .. i cant find ONE (free) jumper in my lab!

6502 progress

Added second VIA chip. (For hex keyboard)

Skipped the sound setups with simple components or the Yamaha chip. Straight to the commodore SID chip. Added a amplifier and a speaker.

Added ROM functions for line printing. Picture with 2 lines, and my name in Japanese

Now I have to wait for components. I’ve made a simulation for a address decoder.

Rest I’ve put in previous posts as updates.

Meanwhile testing 6502 apps on Android


Weird things at work

From a long time ago

(two examples)

There was a place i’ve worked, they did something weird with network masks.
The cause was probably because of changes in the network, and some things had to be re-routed.
When doing routing you use a network mask, this mask is used in tcp/ip routing. When an IP is not in a local network, which boundaries are set by the mask, the protocol will use the gateway to break out of the network.

Example time!

192.168.1.2 – computer IP
192.168.1.0 – network it sees as local
255.255.255.0 – network mask
192.168.1.1 – gateway of example

in binary

11000000.10101000.00000001.00000010 – computer IP
11000000.10101000.00000001.00000000 – network
11111111.11111111.11111111.00000000 – mask (should be al 1’s until the boundary of the network)

The 1’s in the mask should work as a filter!

What i’ve seen was something like a mask
11111111.1111111.00111111.00000000 !
This gave the network a gap into another network!

This is NOT encouraged, don’t do this.
Theoretical and seen in a real live environment .. it CAN work

Another weird one

I was asked to look into a problem at the Johan Cruyff Foundation.
Btw I ran into the guy, but I didn’t know who he was, they had to explain.
(I ‘m not into football)

Some PC’s sometimes could not connect to the network. Sometimes the printer didn’t work.
A colleague of mine looked into it and could not find it.

  • The order in which powered up the PC’s and printer seems to matter.
  • From the 7-8 devices only 6 worked.

So I drove to Amsterdam, turned on a pc, and looked at its network settings.
It was getting a IP, but it was a PUBLIC one!
Looking at another machine, it was also a public one!

The router was locked inside a cabinet, but I knew the famous dutch telecom provider had done something like this! (below)

As it should be (4 ports example)

The organisation had a range of 6 public addresses, thats why not all machines could connect.
These windows pc where connected directly to the internet!
(Some virusscanning required I think!)

74 Series logic, Rom, Gal, Pal, FPGA for Address decoding

For accessing the different components in computers you have to use the Address Bus.
In most 8 bits computers there are 16 address lines.

The CPU on a 6502 can access 65536 addresses (16 bit ). But most chips in the circuit have just a few address lines.
So the chip to use has to be selected using a CE (chip Enable) signal.

Old article i found on my fileserver from 1984

74 Series logic

Above example uses A15 combined with A14 to address the 16K ROM
When using a 32k rom in the upper part of the memory, a15 can be used as CE

The 74ALS133 is a widely used decoder due to it’s many inputs.

Sometimes not all address lines are used for decoding, then you will get a repetition of the device in the memory map.

Above 6522 VIA has only 4 address lines RS0-RS3. But 2 chipselect pins (CS).
If you connect the chip as below.

A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00
CS1 CS2  NC  NC  NC  NC  NC  NC  NC  NC  NC  NC CR3 CR2 CR1 CR0
(NC - not connected, and CS2 is inverted!)

The chip would be selected when A15 is 1 and A14 is 0, A13-A04 it would not listen to. So its 4 bits addresses (total 16), would be repeated in a block $8000-$BFFF (10xx xxxx xxxx aaaa) 16384 addresses for 16 addresses on the 6522

ROM

Another simple solution to get a more precise address decoder without using a lot of components is using a ROM.
But this wil only work for low speeds!
A eeprom is relative cheap

Example ROM as chip enable/select

PAL PLA GAL

With these devices you can “program” a schematic which works as above example’s of the 74 series. But now you can do it using only one component.

PALs and PLAs are fuse-programmed, some are erasable like (e)eprom.
Below a example of the code.
Most of the PAL/PLA/GAL are hard to get and obsolete

;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE    pRAM PC_interface Address Decoder
PATTERN  pRAM97A.pds
REVISION H
AUTHOR   Trevor Clarkson
COMPANY  EEE KCL
DATE     30/05/97

CHIP  decode  PALCE20V8

;---------------------------------- PIN Declarations ---------------
PIN  1          AEN                                   COMBINATORIAL ; INPUT
PIN  2          A9                                    COMBINATORIAL ; INPUT
PIN  3          A8                                    COMBINATORIAL ; INPUT
PIN  4          A7                                    COMBINATORIAL ; INPUT
PIN  5          A6                                    COMBINATORIAL ; INPUT
PIN  6          A5                                    COMBINATORIAL ; INPUT
PIN  7          A4                                    COMBINATORIAL ; INPUT
PIN  8          A3                                    COMBINATORIAL ; INPUT
PIN  9          A2                                    COMBINATORIAL ; INPUT
PIN  10         A1                                    COMBINATORIAL ; INPUT
PIN  11         IOW                                   COMBINATORIAL ; INPUT
PIN  12         GND
PIN  13         IOR                                   COMBINATORIAL ; INPUT
PIN  14         ACK_HALT                              COMBINATORIAL ; INPUT
PIN  15         PLS_EN                                COMBINATORIAL ; OUTPUT
PIN  16         BRDW                                  COMBINATORIAL ; OUTPUT
PIN  17         MOD_CTRL                              COMBINATORIAL ; OUTPUT
PIN  18         RAM_ACCESS                            COMBINATORIAL ; OUTPUT
PIN  19         IO_16                                 COMBINATORIAL ; OUTPUT
PIN  20         LATCH_MOD                             COMBINATORIAL ; OUTPUT
PIN  21         LATCH_ADD                             COMBINATORIAL ; OUTPUT
PIN  22         P300                                  COMBINATORIAL ; OUTPUT
PIN  23         P300IN                                COMBINATORIAL ; INPUT
PIN  24         VCC

;PC address decoding functions (not all in this PAL)
;uses latched address to provide low-order address lines to pRAM/RAM
;       A3      A2      A1      R/W     Addr    Function
;       0       0       0       R       300     MFF_0
;                               W               not used
;       0       0       1       R       302     MFF_1
;                               W               not used
;       0       1       0       R       304     MFF_2
;                               W               not used
;       0       1       1       R       306     MFF_3
;                               W               Latch Module Number
;       1       0       0       R       308     PLS_Status  (pRAM status)
;                               W               PLS_Control (pRAM control)
;       1       0       1       R       30A     Weight/Connection-
;                               W                Pointer RAM access
;       1       1       0       R       30C     not used
;                               W               Latched RAM address
;       1       1       1       R       30E     not used
;                               W               pRAM_256 module control
;
; NB. IO_16 must be tri-stated when not in use

;----------------------------------- Boolean Equation Segment ------
EQUATIONS

/P300 = A9*A8*/A7*/A6*/A5*/A4*/IOR + A9*A8*/A7*/A6*/A5*/A4*/IOW

/BRDW = /P300IN * /IOW

/PLS_EN = /P300IN*/A3*/IOR + /P300IN*A3*/A2*/A1

; MOD_CTRL is active HIGH
MOD_CTRL = ACK_HALT * /BRDW * A3 * A2 * A1 * /IOW

; RAM_ACCESS is active HIGH
RAM_ACCESS = ACK_HALT * /P300IN * A3 * /A2 * A1

IO_16 = GND
IO_16.TRST = /P300IN
; enable 16-bit transfers

; LATCH_MOD is active HIGH
LATCH_MOD = /BRDW * /A3 * A2 * A1

; LATCH_ADD is active HIGH
LATCH_ADD = /BRDW * A3 * A2 * /A1

;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON A9 A8 A7 A6 A5 A4 IOR /IOW /BRDW /PLS_EN MOD_CTRL RAM_ACCESS IO_16 LATCH_MOD LATCH_ADD ACK_HALT /P300 /P300IN
SETF /A9 /A8 /A7 /A6 /A5 /A4 /A3 /A2 /A1 IOR IOW /ACK_HALT /P300IN
SETF /IOW ; test P300 doesn't respond
SETF IOW /IOR ; test P300 doesn't respond
SETF IOR
SETF A9 A8 /A7 /A6 /A5 /A4 /IOR /P300IN
SETF A1
SETF A2 /A1
SETF A1 ; read mff0-3
SETF IOR /IOW ; test P300 and BRDW
SETF /A3 A2 A1 ; test Latch Module No
SETF IOW A3 A2 A1 ; MOD-CTRL not active until ACK_HALT
SETF ACK_HALT /IOW
SETF IOW /ACK_HALT
SETF A3 /A2 A1 ; check RAM_ACCESS
SETF ACK_HALT /IOW
SETF /ACK_HALT IOW
SETF ACK_HALT /IOR ; check READ and WRITE to RAM
SETF IOR P300IN
SETF /A3 A2 A1
SETF /ACK_HALT /P300IN
SETF IOW
SETF /A3 A2 A1 /IOW ; check LATCH_MOD 
SETF IOW
SETF A3 A2 /A1
SETF /IOW       ; check LATCH_ADD
SETF /A3 /A2 /A1 ; shouldn't happen normally

TRACE_OFF
;-------------------------------------------------------------------

FPGA

Example FPGA code. A solution which is too fancy for my 6502.
// Verilog code for decoder 
// 5-input AND gate 
module AND_5_input(g,a,b,c,d,e);
  output g;
  input a,b,c,d,e;
  and #(50) and1(f1,a,b,c,d),
            and2(g,f1,e);
endmodule
// fpga4student.com: FPGA projects, Verilog projects, VHDL projects 
// Verilog code for decoder 
// Decoder top level Verilog code using 5-input AND gates 
module dec5to32(Out,Adr);
input [4:0] Adr; // Adr=Address of register
output [31:0] Out;
not #(50) Inv4(Nota, Adr[4]);
not #(50) Inv3(Notb, Adr[3]);
not #(50) Inv2(Notc, Adr[2]);
not #(50) Inv1(Notd, Adr[1]);
not #(50) Inv0(Note, Adr[0]);

AND_5_input a0(Out[0],  Nota,Notb,Notc,Notd,Note); // 00000
AND_5_input a1(Out[1],  Nota,Notb,Notc,Notd,Adr[0]); // 00001
AND_5_input a2(Out[2],  Nota,Notb,Notc,Adr[1],Note); //00010
AND_5_input a3(Out[3],  Nota,Notb,Notc,Adr[1],Adr[0]);
AND_5_input a4(Out[4],  Nota,Notb,Adr[2],Notd,Note);
AND_5_input a5(Out[5],  Nota,Notb,Adr[2],Notd,Adr[0]);
AND_5_input a6(Out[6],  Nota,Notb,Adr[2],Adr[1],Note);
AND_5_input a7(Out[7],  Nota,Notb,Adr[2],Adr[1],Adr[0]);
AND_5_input a8(Out[8],    Nota,Adr[3],Notc,Notd,Note);
AND_5_input a9(Out[9],    Nota,Adr[3],Notc,Notd,Adr[0]);
AND_5_input a10(Out[10],  Nota,Adr[3],Notc,Adr[1],Note);
AND_5_input a11(Out[11],  Nota,Adr[3],Notc,Adr[1],Adr[0]);
AND_5_input a12(Out[12],  Nota,Adr[3],Adr[2],Notd,Note);
AND_5_input a13(Out[13],  Nota,Adr[3],Adr[2],Notd,Adr[0]);
AND_5_input a14(Out[14],  Nota,Adr[3],Adr[2],Adr[1],Note);
AND_5_input a15(Out[15],  Nota,Adr[3],Adr[2],Adr[1],Adr[0]);
AND_5_input a16(Out[16],  Adr[4],Notb,Notc,Notd,Note);
AND_5_input a17(Out[17],  Adr[4],Notb,Notc,Notd,Adr[0]);
AND_5_input a18(Out[18],  Adr[4],Notb,Notc,Adr[1],Note);
AND_5_input a19(Out[19],  Adr[4],Notb,Notc,Adr[1],Adr[0]);
AND_5_input a20(Out[20],  Adr[4],Notb,Adr[2],Notd,Note);
AND_5_input a21(Out[21],  Adr[4],Notb,Adr[2],Notd,Adr[0]);
AND_5_input a22(Out[22],  Adr[4],Notb,Adr[2],Adr[1],Note);
AND_5_input a23(Out[23],  Adr[4],Notb,Adr[2],Adr[1],Adr[0]);
AND_5_input a24(Out[24],  Adr[4],Adr[3],Notc,Notd,Note);
AND_5_input a25(Out[25],  Adr[4],Adr[3],Notc,Notd,Adr[0]);
AND_5_input a26(Out[26],  Adr[4],Adr[3],Notc,Adr[1],Note);
AND_5_input a27(Out[27],  Adr[4],Adr[3],Notc,Adr[1],Adr[0]);
AND_5_input a28(Out[28],  Adr[4],Adr[3],Adr[2],Notd,Note);
AND_5_input a29(Out[29],  Adr[4],Adr[3],Adr[2],Notd,Adr[0]);
AND_5_input a30(Out[30],  Adr[4],Adr[3],Adr[2],Adr[1],Note);
AND_5_input a31(Out[31],  Adr[4],Adr[3],Adr[2],Adr[1],Adr[0]); // 11111
endmodule

Example of Ice studio FPGA programming

Conslusion:

For now i will use the 74 logic. But i definitely will revisit FPGA’s

G1200 Microscope

Another good suggestion by Bigred.

We are all getting older and electronics smaller. It’s hard to see if your soldering blobs are okay!
Those blobs can reflect the light in a way that it’s not visible anymore to check them.

So i took Bigreds advice, and bought a G1200 Microscope.
It’s a cheap but helpfull little gadget.

  • 1-1200 times zoom
  • 7inch screen (720p)
  • SDcard
  • Lipo battery
  • Recording on micro sdcard in 12 mega pixels pictures and 1080P Video.
    (even got a timer)
  • Focus button, and extra lights (There is a light source in de camera head, which can be adjusted by a knob)
  • When connecting to your pc, you get 3 options
    • PC Camera ( … so you can record using your pc with for example OBS)
    • Mass Storage, to read the SDCARD
    • Rec_mode ?!? – No idea yet

Below some examples:

Picture example
Video example

SDCard Access:

Access to the sdcard is a little hard. Connecting via Mass Storage is a solution. But i’ve put a little piece of tape to get the card in or out of the slot.

You can view the recordings on the Microscope itself. So i was wondering, can it play any other movie files?

I placed different MOV files on the sdcard, but the microscope skipped the ones i places on the sdcard myself.

I started to look at the metadata, and saw a Codec ID
“qt 2016.04.21 (qt )”

 mediainfo VID_001.MOV
General
Complete name                            : VID_001.MOV
Format                                   : MPEG-4
Format profile                           : QuickTime
Codec ID                                 : qt   2016.04.21 (qt  )
File size                                : 551 MiB
Duration                                 : 12s 0ms
Overall bit rate                         : 385 Mbps
Encoded date                             : UTC 1904-01-01 00:00:00
Tagged date                              : UTC 1904-01-01 00:00:00

Video
ID                                       : 1
Format                                   : AVC
Format/Info                              : Advanced Video Codec
Format profile                           : Main@L4.1
Format settings, CABAC                   : Yes
Format settings, ReFrames                : 1 frame
Codec ID                                 : avc1
Codec ID/Info                            : Advanced Video Coding
Duration                                 : 12s 0ms
Source duration                          : 12s 360ms
Bit rate                                 : 14.5 Mbps
Width                                    : 1 920 pixels
Height                                   : 1 080 pixels
Display aspect ratio                     : 16:9
Frame rate mode                          : Constant
Frame rate                               : 25.000 fps
Color space                              : YUV
Chroma subsampling                       : 4:2:0
Bit depth                                : 8 bits
Scan type                                : Progressive
Bits/(Pixel*Frame)                       : 0.280
Stream size                              : 20.8 MiB (4%)
Source stream size                       : 21.3 MiB (4%)
Language                                 : 33
Encoded date                             : UTC 1904-01-01 00:00:00
Tagged date                              : UTC 1904-01-01 00:00:00
mdhd_Duration                            : 12000

Audio
ID                                       : 2
Format                                   : PCM
Format settings, Endianness              : Little
Format settings, Sign                    : Signed
Codec ID                                 : sowt
Duration                                 : 12s 0ms
Source duration                          : 12s 288ms
Bit rate mode                            : Constant
Bit rate                                 : 128 Kbps
Channel(s)                               : 1 channel
Channel positions                        : Front: C
Sampling rate                            : 8 000 Hz
Bit depth                                : 16 bits
Stream size                              : 188 KiB (0%)
Source stream size                       : 192 KiB (0%)
Language                                 : 33
Default                                  : Yes
Alternate group                          : 1
Encoded date                             : UTC 1904-01-01 00:00:00
Tagged date                              : UTC 1904-01-01 00:00:00

Tried to change this with ffmpeg, but it would not change the way i want.

ffmpeg -i VID_002.MOV -c copy -map 0 -brand 'qt   2016.04.21 (qt  )' VID_007.MOV

mediainfo VID_007.MOV
General
Complete name                            : VID_007.MOV
Format                                   : MPEG-4
Format profile                           : QuickTime
Codec ID                                 : qt   0000.02 (qt  )  <--------------- nope

Header of the movie clip
maybe i have to look into this … later

00000000  00 00 00 14 66 74 79 70  71 74 20 20 20 16 04 21  |....ftypqt   ..!|
00000010  71 74 20 20 00 00 00 08  77 69 64 65 01 57 c7 e4  |qt  ....wide.W..|
00000020  6d 64 61 74 00 00 01 d8  0c 00 00 00 4a 4b 4c 4a  |mdat........JKLJ|
00000030  19 00 00 00 80 07 00 00  38 04 00 00 01 00 00 00  |........8.......|
00000040  10 00 00 00 40 1f 00 00  00 20 00 00 01 00 00 00  |....@.... ......|
00000050  0c 00 00 00 73 6f 77 74  00 02 00 00 00 00 00 00  |....sowt........|
00000060  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|

Memory map generator

Started to write a program to generate a memory map like this

It will be a python script which generates a ascii table.

| a15 | a14 | a13 | a12 | a11 | a10 | a09 | a08 | a07 | a06 | a05 | a04 | a03 | a02 | a01 | a00 |
|  1  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  | ROM
|  0  |  0  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  | RAM
|  0  |  1  |  1  |  x  |  x  |  x  |  x  |  x  |  x  |  x  |  x  |  x  |  a  |  a  |  a  |  a  | VIA
|  0  |  0  |  0  |  0  |  0  |  0  |  0  |  1  |  a  |  a  |  a  |  a  |  a  |  a  |  a  |  a  | PS

Above example shows:

  • Rom – $8000 and up
  • Ram – $0000 till $3FFF
  • Via chip – $6xxx-$7xxxx 16 addresses repeating in this block.
    This will be the interesting/hard part
  • Program stack – in RAM – $0100-$01FF

Generated output

| 0000 | ram |     |     |      |      |
| 00ff | ram |     |     |      |      |
| 0100 | ram |     | ps  |      |      |
| 01ff | ram |     | ps  |      |      |
| 0200 | ram |     |     |      |      |
| 3fff | ram |     |     |      |      |
| 4000 |     |     |     |      |      |
| 5fff |     |     |     |      |      |
| 6000 |     |     |     | via1 |      |
| 6fff |     |     |     | via1 |      |
| 7000 |     |     |     |      | via2 |
| 7fff |     |     |     |      | via2 |
| 8000 |     | rom |     |      |      |
| ffff |     | rom |     |      |      |
#!/bin/python

# 0 = address should be 0 .. Duh
# 1 = address should be 1 .. Duh
# a = address 0 or 1
# x = not connected, future function

# try
#via1 = ["0","1","1","0","x","x","x","x","x","x","0","x","a","a","a","a"]

rom = ["1","a","a","a","a","a","a","a","a","a","a","a","a","a","a","a"]
ram = ["0","0","a","a","a","a","a","a","a","a","a","a","a","a","a","a"]
via1 = ["0","1","1","0","x","x","x","x","x","x","x","x","a","a","a","a"]
via2 = ["0","1","1","1","x","x","x","x","x","x","x","x","a","a","a","a"]
ps  = ["0","0","0","0","0","0","0","1","a","a","a","a","a","a","a","a"]

counter = 0
prevhexw = f"{0:04x}"

prevram = "nix"
prevrom = "nix"
prevps = "nix"
prevvia1 = "nix"
prevvia2 = "nix"

while counter < 65536:
    binw = f"{counter:016b}"
    hexw = f"{counter:04x}"
    binint = bin(int(counter))
    address=0

    ramcheck=0    
    romcheck=0    
    pscheck=0
    via1check=0
    via2check=0

    printram = "   "
    printrom = "   "
    printps = "   "
    printvia1 = "    "
    printvia2 = "    "
    myram=ram.copy()
    myrom=rom.copy()
    myps=ps.copy()
    myvia1=via1.copy()
    myvia2=via2.copy()
    while address < 16:

        if myram[address] == "a":
            myram[address]=binw[address]
        if myram[address] == "x":
            myram[address]=binw[address]
        if myram[address] != binw[address]:
            ramcheck=1

        if myrom[address] == "a":
            myrom[address]=binw[address]
        if myrom[address] == "x":
            myrom[address]=binw[address]
        if myrom[address] != binw[address]:
            romcheck=1

        if myps[address] == "a":
            myps[address]=binw[address]
        if myps[address] == "x":
            myps[address]=binw[address]
        if myps[address] != binw[address]:
            pscheck=1

        if myvia1[address] == "a":
            myvia1[address]=binw[address]
        if myvia1[address] == "x":
            myvia1[address]=binw[address]
        if myvia1[address] != binw[address]:
            via1check=1

        if myvia2[address] == "a":
            myvia2[address]=binw[address]
        if myvia2[address] == "x":
            myvia2[address]=binw[address]
        if myvia2[address] != binw[address]:
            via2check=1


        address=address+1

    if ramcheck==0:
        printram="ram"
    if romcheck==0:
        printrom="rom"
    if pscheck==0:
        printps="ps "
    if via1check==0:
        printvia1="via1"
    if via2check==0:
        printvia2="via2"


    if prevram != printram or prevrom != printrom or prevps != printps or prevvia1 != printvia1 or prevvia2 != printvia2:
        printlinep = f"| {prevhexw} | {prevram} | {prevrom} | {prevps} | {prevvia1} | {prevvia2} |"
        printline = f"| {hexw} | {printram} | {printrom} | {printps} | {printvia1} | {printvia2} |"
        if prevram != "nix":
            print(printlinep)
        print(printline)
    prevram=printram
    prevrom=printrom
    prevps=printps
    prevvia1=printvia1
    prevvia2=printvia2
    prevhexw=hexw
    counter=counter+1;
printline = f"| {hexw} | {printram} | {printrom} | {printps} | {printvia1} | {printvia2} |"
print(printline)

Scavenging parts and schematics

Searching for parts .. from other projects

I want to make a new clock module using a bare ATmega328 running on a 16mhz crystal. This to provide a clock for my 6502 computer.

Using a display and a rotary encoder I want to create a clock module which generates a 50/50 duty cycle clock 1Hz – 1 MHz.

Input module for my 6502 will be 5 buttons. (For now) that’s what’s left on the VIA on port A. (Rest is used by the display). The display i’m going to place directly on the bus. But I already ordered a second VIA.  Matrix keyboard will be next. Then I will use the buttons in the picture for shift/alternate buttons. Because I’ll need about 25 keys. (See other posts) . I’ll probably end up making that one myself.

Badge picture plus sound in micropython

python mch2022-tools/webusb_fat_dir.py /flash/apps/python/easy
for f in easy.mp3 easy.png icon.png __init__.py ; do python  mch2022-tools/webusb_fat_push.py $f /flash/apps/python/easy/$f ; done

Micropython code __init__.py

mport display
import mch22
from audio import play
import buttons
from time import sleep
from machine import Pin
from neopixel import NeoPixel

powerPin = Pin(19, Pin.OUT)
dataPin = Pin(5, Pin.OUT)
np = NeoPixel(dataPin, 5)
powerPin.on()


def on_home_btn(pressed):
  if pressed:
    mch22.exit_python()


display.drawPng(0,0,"/apps/python/easy/easy.png")
display.flush()



# Led setup
#   2   3    
#      1
#     0     4

np[0] = (23,5,15)
np[1] = (3,15,22)
np[2] = (25,24,1)
np[3] = (25,24,1)
np[4] = (23,4,15)
np.write()


buttons.attach(buttons.BTN_HOME, on_home_btn)
# playing with volume 0 to wakeup sound device, else it is going to clip
play('/apps/python/easy/easy.mp3', volume=0)
sleep(7)
while True:
    play('/apps/python/easy/easy.mp3', volume=100)
    sleep(30)

"If something is worth doing, it's worth overdoing."