Address decoding with split IO

Last Updated or created 2022-09-07

Made a simulation of my new address decoder.
It uses a 74LS138 and a bunch of NAND gates.
You can safe using 4 NAND gates if you are not going to use split IO

7000-7FFFSound chipSID
6000-6FFFDisplay + cursorVIA1
4800-4FFFsplit ioIO
4000-47FFsplit ioIO – ACIA
0000-3FFFUses clockRAM
Above part is a single chip 74LS138

UPDATE: Found some 74LS139, so i could have changed some things around.

Simplified schematic 74LS139

Try it over here: