Above is my design for a hex keyboard to enter opcodes in hex using a simple monitor program. i used a 74ls922 which can decode a 4×4 matrix. I’d rather had a 74ls723 which can encode 20 keys.
Nowhere to be found. So i have to think of a new plan.
Now it is configured as follows:
C
D
E
F
8
9
A
B
4
5
6
7
0
1
2
3
When pressing the alternate key
addr (to implement)
run (1/2 implemented)
reset (to implement)
step instruction (to implement)
memory next
memory previous
PCB design for matrix hexboard with place for notes
Meanwhile i’ve ordered new keys (the ones i’ve been using for my photomanager project and wnat to have a setup like this:
?
?
addr
run
reset
C
D
E
F
?
8
9
A
B
step
4
5
6
7
mem next
0
1
2
3
mem prev
When you want to show the status of busses and alike, you can’t use a led and restistor directly on the bus, it will require too much current. So i’ve been using below schematic which uses a darlington array.
Now i can display databus, address bus and i’ve been using this for address decoding logic and hex keyboard.
I’ve implemented a second VIA chip, and ordered components to amplify the SID sound part
Above is my Kicad design (reverse engineering print below, which was made for my 6802CPU, which i could use to test the 6822 PIA) The 6822 is simular to 6502 in design. So i’m going to redo this for my 6502. The 7 segment displays are a start of hex-keyboard/display combo i’m going to post more of in the next days.
Below a part of the rom for the LCD dual line display.
Part of the ROM assembly code, top part is text (o.a. japanese)
Started to write routines which i can call to manipulate the display. Setting the pointer to a message, setting the line to use and a subset of controlls like: Center, Right, binary to ascii, scrolling, etcetera
lda #0 ; set line number
sta lineno ; store
jsr gotoline ; goto line in display
lda #<message ; get address from message and store for printline subroutine
sta messagestore
lda #>message
sta messagestore+1
jsr printline ; print
lda #1 ; set line number
sta lineno ; store
jsr gotoline
lda #<message2
sta messagestore
lda #>message2
sta messagestore+1
jsr printline
Above additions: New address decoder Below left the new graphical display, below right a test board which shows address lines and decoded chip-enable lines.
A15 high -> ROM A15 && A14 low -> RAM combination of A15 low and A14 high – A13 and A12 wil select peripherals.
Adress decoding
Start of a wirewrapped version
Above is a start of a wirewrapped version, i also started a PCB design in KIcad that will continuously be changed as i alter designs.
UPDATE SID Working! Using new address decoder.
SID = $7000
makesound:
lda #0
sta SID+$5 ; Channel1 - attack/decay
lda #250
sta SID+$6 ; Channel1 - Sustain/Release
lda #$95
sta SID+$0 ; Channel1 - Frequency low-byte
lda #$44
sta SID+$1 ; Channel1 - Frequency high-byte
lda #%00100001
sta SID+$4 ; SAW + Gate
lda #$0f
sta SID+$18 ; Volume max
For accessing the different components in computers you have to use the Address Bus. In most 8 bits computers there are 16 address lines.
The CPU on a 6502 can access 65536 addresses (16 bit ). But most chips in the circuit have just a few address lines. So the chip to use has to be selected using a CE (chip Enable) signal.
Old article i found on my fileserver from 1984
74 Series logic
Above example uses A15 combined with A14 to address the 16K ROM When using a 32k rom in the upper part of the memory, a15 can be used as CE
The 74ALS133 is a widely used decoder due to it’s many inputs.
Sometimes not all address lines are used for decoding, then you will get a repetition of the device in the memory map.
Above 6522 VIA has only 4 address lines RS0-RS3. But 2 chipselect pins (CS). If you connect the chip as below.
The chip would be selected when A15 is 1 and A14 is 0, A13-A04 it would not listen to. So its 4 bits addresses (total 16), would be repeated in a block $8000-$BFFF (10xx xxxx xxxx aaaa) 16384 addresses for 16 addresses on the 6522
ROM
Another simple solution to get a more precise address decoder without using a lot of components is using a ROM. But this wil only work for low speeds! A eeprom is relative cheap
Example ROM as chip enable/select
PAL PLA GAL
With these devices you can “program” a schematic which works as above example’s of the 74 series. But now you can do it using only one component.
PALs and PLAs are fuse-programmed, some are erasable like (e)eprom. Below a example of the code. Most of the PAL/PLA/GAL are hard to get and obsolete
;PALASM Design Description
;---------------------------------- Declaration Segment ------------
TITLE pRAM PC_interface Address Decoder
PATTERN pRAM97A.pds
REVISION H
AUTHOR Trevor Clarkson
COMPANY EEE KCL
DATE 30/05/97
CHIP decode PALCE20V8
;---------------------------------- PIN Declarations ---------------
PIN 1 AEN COMBINATORIAL ; INPUT
PIN 2 A9 COMBINATORIAL ; INPUT
PIN 3 A8 COMBINATORIAL ; INPUT
PIN 4 A7 COMBINATORIAL ; INPUT
PIN 5 A6 COMBINATORIAL ; INPUT
PIN 6 A5 COMBINATORIAL ; INPUT
PIN 7 A4 COMBINATORIAL ; INPUT
PIN 8 A3 COMBINATORIAL ; INPUT
PIN 9 A2 COMBINATORIAL ; INPUT
PIN 10 A1 COMBINATORIAL ; INPUT
PIN 11 IOW COMBINATORIAL ; INPUT
PIN 12 GND
PIN 13 IOR COMBINATORIAL ; INPUT
PIN 14 ACK_HALT COMBINATORIAL ; INPUT
PIN 15 PLS_EN COMBINATORIAL ; OUTPUT
PIN 16 BRDW COMBINATORIAL ; OUTPUT
PIN 17 MOD_CTRL COMBINATORIAL ; OUTPUT
PIN 18 RAM_ACCESS COMBINATORIAL ; OUTPUT
PIN 19 IO_16 COMBINATORIAL ; OUTPUT
PIN 20 LATCH_MOD COMBINATORIAL ; OUTPUT
PIN 21 LATCH_ADD COMBINATORIAL ; OUTPUT
PIN 22 P300 COMBINATORIAL ; OUTPUT
PIN 23 P300IN COMBINATORIAL ; INPUT
PIN 24 VCC
;PC address decoding functions (not all in this PAL)
;uses latched address to provide low-order address lines to pRAM/RAM
; A3 A2 A1 R/W Addr Function
; 0 0 0 R 300 MFF_0
; W not used
; 0 0 1 R 302 MFF_1
; W not used
; 0 1 0 R 304 MFF_2
; W not used
; 0 1 1 R 306 MFF_3
; W Latch Module Number
; 1 0 0 R 308 PLS_Status (pRAM status)
; W PLS_Control (pRAM control)
; 1 0 1 R 30A Weight/Connection-
; W Pointer RAM access
; 1 1 0 R 30C not used
; W Latched RAM address
; 1 1 1 R 30E not used
; W pRAM_256 module control
;
; NB. IO_16 must be tri-stated when not in use
;----------------------------------- Boolean Equation Segment ------
EQUATIONS
/P300 = A9*A8*/A7*/A6*/A5*/A4*/IOR + A9*A8*/A7*/A6*/A5*/A4*/IOW
/BRDW = /P300IN * /IOW
/PLS_EN = /P300IN*/A3*/IOR + /P300IN*A3*/A2*/A1
; MOD_CTRL is active HIGH
MOD_CTRL = ACK_HALT * /BRDW * A3 * A2 * A1 * /IOW
; RAM_ACCESS is active HIGH
RAM_ACCESS = ACK_HALT * /P300IN * A3 * /A2 * A1
IO_16 = GND
IO_16.TRST = /P300IN
; enable 16-bit transfers
; LATCH_MOD is active HIGH
LATCH_MOD = /BRDW * /A3 * A2 * A1
; LATCH_ADD is active HIGH
LATCH_ADD = /BRDW * A3 * A2 * /A1
;----------------------------------- Simulation Segment ------------
SIMULATION
TRACE_ON A9 A8 A7 A6 A5 A4 IOR /IOW /BRDW /PLS_EN MOD_CTRL RAM_ACCESS IO_16 LATCH_MOD LATCH_ADD ACK_HALT /P300 /P300IN
SETF /A9 /A8 /A7 /A6 /A5 /A4 /A3 /A2 /A1 IOR IOW /ACK_HALT /P300IN
SETF /IOW ; test P300 doesn't respond
SETF IOW /IOR ; test P300 doesn't respond
SETF IOR
SETF A9 A8 /A7 /A6 /A5 /A4 /IOR /P300IN
SETF A1
SETF A2 /A1
SETF A1 ; read mff0-3
SETF IOR /IOW ; test P300 and BRDW
SETF /A3 A2 A1 ; test Latch Module No
SETF IOW A3 A2 A1 ; MOD-CTRL not active until ACK_HALT
SETF ACK_HALT /IOW
SETF IOW /ACK_HALT
SETF A3 /A2 A1 ; check RAM_ACCESS
SETF ACK_HALT /IOW
SETF /ACK_HALT IOW
SETF ACK_HALT /IOR ; check READ and WRITE to RAM
SETF IOR P300IN
SETF /A3 A2 A1
SETF /ACK_HALT /P300IN
SETF IOW
SETF /A3 A2 A1 /IOW ; check LATCH_MOD
SETF IOW
SETF A3 A2 /A1
SETF /IOW ; check LATCH_ADD
SETF /A3 /A2 /A1 ; shouldn't happen normally
TRACE_OFF
;-------------------------------------------------------------------
FPGA
Example FPGA code. A solution which is too fancy for my 6502.
I want to make a new clock module using a bare ATmega328 running on a 16mhz crystal. This to provide a clock for my 6502 computer.
Using a display and a rotary encoder I want to create a clock module which generates a 50/50 duty cycle clock 1Hz – 1 MHz.
Input module for my 6502 will be 5 buttons. (For now) that’s what’s left on the VIA on port A. (Rest is used by the display). The display i’m going to place directly on the bus. But I already ordered a second VIA. Matrix keyboard will be next. Then I will use the buttons in the picture for shift/alternate buttons. Because I’ll need about 25 keys. (See other posts) . I’ll probably end up making that one myself.
I found examples like this, rest i have to think of myself
{funny story] In 2019 i wanted to make a simple probe, which could detect 0 or 1 or a pulse. I wanted to make this on a little print using wirewrap wires and IC sockets. (I still have the tool which i used in the 90s.) When going to a well-known electronics shop in Den Hague. A great shop to get all kinds of oldskool electronics. But i’m getting ahead of the story. This shop has a lot of components for all kinds of electronics. New and what it looked like de-soldered component from boards or bought from old going-out-of-business shops or factories. Stuff you needed for 60s equipment. Well i was at the counter, asking a old guy. “Do you have wire-wrap wire” He said: ” No that’s old skool” …. {/funny story]
Latest wirewrap only a few years agoFrontToolsIn front the wirewrap sockets, I even had ZIF sockets (at the back) with long pins for wirewrapping.Ugly back from print
The wirewrap tool has a cable stripper. After stripping you would put a short part in the tool, place the tool over a IC pin and turning would wrap the wire on the pins. You could stack multiple connections on one pin. Removing could be done by turning the tool counterclockwise. Sometimes you had to remove the one closest to the print, replacing all wires. (Or cut the wrong/not needed wire and leave it in place … )
I’m thinking of moving my breadboard 6502 to a wirewrapped version. All my old boards are gone .. before i got a digital camera .. 🙁
Flashing ROMs .. (eeproms). It used to be a pain in the *$$. Burning took a looong time. But clearing one with UV took .. 20 minutes or so. Using one of these:
Altered clock module
Changed button press
Dipswitches for more speed control (red .. upper left)
Changed Rom/Ram
Changed addressing
Added RAM
ZIF Socket for ROM
VIC 6522
Fixed clock
Added buttons for interrupt
Display
Display works now
To test: Create Address logic to access display without VIA Can work, but not at high speed clock. Stays behind VIA
To buy: st7920 lcd 128×64
Generic improvements
Rewired most parts, using color codes (Blue data, Yellow Address and so on)
Added leds on data and address bus using ULN2803 darlington arrays
100nF Decoupling capacitors on the power rails
To do’s or ‘have to look into’s’
For sound i planned to use a General Instrument AY-3-8910, it is somewhere in my Lab, i know it is. I saved this chip and a SID for my Amiga addon soundcard. Where are my plans for the simple v1 setup? (FOUND IT)
I have to start writing rom functions for display usage. Like JSR $ff00 – Clear screen subroutine .. etc
I’m scraping information from websites, to get started on my clock controller. ATmega328 with ssd1306 display and rotary encoder/dip switches
Notes about the movie: Left side is Arduino IDE monitor reading Addressbus and Databus. (I’m going to try to rewrite this to realtime disassemble) Resetting system. Stepping CPU with manual clock pulses. Start vector being read at $FFFC/$FFFD. Program being run from $8000. Set clock on automatic ( ~ about 150 Hz ) Last opcodes you see a JMP loop 4C 2F 80, that is JMP $802F Display enlarged on video, was not visible on movie i took on mobile. (Wrong angle?)
Breadboard overview
Clock module
Reset module + Crystal
CPU + nmi/int buttons
RAM and ROM
Address decode + Bus divide
Addres/Data bus leds
6522 VIA + Display
2nd via + Buttons
?
(sound board)
TIL: 6502 can run without ram only rom,expect when using JSR … which uses a program stack in RAM
Cartridge printEeproms 8k and 32k (also for 6502 project)Eeprom programmer
I’ve got the tools and Bigred made me enthusiastic again. My goal is to make a C64 Cartridge from a PRG. And Not any program, it is the 8085 Emulator from Sepp.
Serveral problems i have to ‘fix’
The program is 17K, Cartridges can only be 16K. So i have to use 2x 8K and compress the data. This means it have to be uncompressed at start time. ( I was thinking of using exomiser for this )
Program starts normally at $0820 and probably is not optimised to run anywhere else. So a starting routine has to copy the program from cartridge memory to the correct location
Luckily i have the source! How cool is that
For version 4.73 it states : Starting at $0820 .. but my hexdump is off by one??!?
00000020 00 20 ec starts with 00 at $0020 .. and not 20 ?!?!
Tools used until now:
Vice – C64 Emulator x64 -cartcrt 8085.crt
c1541 – Linux disk tool for C64 images. Used this to extract the 8085emulator PRG
prg2crt.py – a convertor from PRG to a cartrid file which can be used by Vice python2 prg2crt.py 8085.prg 8085.crt
minipro – eeprom programming tool for Linux minipro -p AT28C64 -w /tmp/test.bin
cartconv (tool from vice to convert crt <-> bin) cartconv -t normal -i test.bin -n ‘my cart’ -o test.crt
xa – Cross assembler 65xx/R65C02/65816
ACME – the ACME Crossassembler for Multiple Environments
Memory Map C64 – source c64-wiki.com
Card Low starts at $8000, so that’s the place where those roms are going to be. To place on this address:
Copy routine : from ($8000 + this copy routine) to $0820 When to decompress?? jmp routine to $0820
A cartridge file >16K and with his emulation headers seems to work??!
Also nice: Magic Desk Cartridge Generator V3.0
UPDATE: 20220811
exomizer sfx 0x0820 8085.prg -o data.exo # Compress and start at 0x0820
xa frame.asm -o frame.bin # Add code and write binary
x64 --cart16 frame.bin # Test cartridge with Vice
frame.asm
;----------------------------------------------------------
; example usage
; xa frame.asm -o frame.bin
; cartconv -t normal -i frame.bin -n 'my cart' -o frame.crt
; x64 -cartcrt frame.crt
;----------------------------------------------------------
;no load-adress for bin-file, so no header here
*=$8000
.word launcher ;cold start
.word launcher ;warm start
.byte $c3 ;c
.byte $c2 ;b
.byte $cd ;m
.byte $38 ;8
.byte $30 ;0
launcher
stx $d016
jsr $fda3 ;prepare irq
jsr $fd50 ;init memory
jsr $fd15 ;init i/o
jsr $ff5b ;init video
;make sure this sets up everything you need,
;the calls above are probably sufficient
ldx #$fb
txs
;set up starting code outside of cartridge-area
move_starter
ldx #(starter_end-starter_start)
loop1
lda starter_start,x
sta $100,x
dex
bpl loop1
jmp $100
;---------------------------------
starter_start
ldx #$40 ;64 pages = 256 * 64 = 16384 Bytes
ldy #0
loop
src
lda exomized_data,y
dst
sta $801,y
iny
bne loop
inc src+2-starter_start+$100
inc dst+2-starter_start+$100
dex
bpl loop
;make sure settings for $01 and IRQ etc are correct for your code
;remember THIS table from AAY64:
; Bit+-------------+-----------+------------+
; 210| $8000-$BFFF |$D000-$DFFF|$E000-$FFFF |
; +---+---+-------------+-----------+------------+
; | 7 |111| Cart.+Basic | I/O | Kernal ROM |
; +---+---+-------------+-----------+------------+
; | 6 |110| RAM | I/O | Kernal ROM |
; +---+---+-------------+-----------+------------+
; | 5 |101| RAM | I/O | RAM |
; +---+---+-------------+-----------+------------+
; | 4 |100| RAM | RAM | RAM |
; +---+---+-------------+-----------+------------+
; | 3 |011| Cart.+Basic | Char. ROM | Kernal ROM |
; +---+---+-------------+-----------+------------+
; | 2 |010| RAM | Char. ROM | Kernal ROM |
; +---+---+-------------+-----------+------------+
; | 1 |001| RAM | Char. ROM | RAM |
; +---+---+-------------+-----------+------------+
; | 0 |000| RAM | RAM | RAM |
; +---+---+-------------+-----------+------------+
lda #$35 ;cart is always on instead of BASIC unless it can be switched off via software
sta $01
jmp $80d ;for exomizer, i.e.
starter_end
;----------------------------------
exomized_data
.bin 2,0,"data.exo"
;syntax for exomizer 2.0.1:
;exomizer sfx sys game.prg -o data.exo
main_file_end
;fill up full $4000 bytes for bin file ($c000-$8000=$4000)
.dsb ($c000-main_file_end),0
Exomiser info
Reading "8085.prg", loading from $0801 to $4CE9.
Crunching from $0801 to $4CE9.
Phase 1: Instrumenting file
-----------------------------
Length of indata: 17640 bytes.
[building.directed.acyclic.graph.building.directed.acyclic.graph.]
Instrumenting file, done.
Phase 2: Calculating encoding
-----------------------------
pass 1: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80273.0 bits ~10035 bytes
pass 2: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80039.0 bits ~10005 bytes
pass 3: optimizing ..
Calculating encoding, done.
Phase 3: Generating output file
------------------------------
Encoding: 1101112133423160,1122,2010223445667788,032144406789BBCD
Length of crunched data: 10034 bytes.
Crunched data reduced 7606 bytes (43.12%)
Target is self-decrunching C64 executable,
jmp address $0820.
Writing "data.exo" as prg, saving from $0801 to $304C.
Memory layout: |Start |End |
Crunched data | $07E7| $2F18|
Decrunched data | $0801| $4CE9|
Decrunch table | $0334| $03D0|
Decruncher | $00FD| $01C0| and $9F,$A7,$AE,$AF
Decrunch effect writes to $DBE7.
Decruncher: |Enter |During|Exit |
RAM config | $37| $37| $37|
IRQ enabled | 1| 1| 1|
UPDATE:20230126
; CODE COPY FROM http://www.lemon64.com/forum/viewtopic.php?t=60786&sid=2559442c8b963d7aac27cb13b493f372
; Thanks for posting: Richard of TND
; this is for a 16KB cart, using ACME!!
!to "mycart.crt",cart16crt
scr = $0400
DecrunchADDR = 2061 ;SYS 2061 (HEX $080D)
*=$8000
!word launcher
!word launcher
!byte $c3,$c2,$cd,$38,$30 ;CBM 80
launcher
sei
stx $d016
jsr $fda3 ;prepare irq
jsr $fd50 ;input memory
jsr $fd15 ;initialise i/o
jsr $ff5b ;initialise video memory
;For a more professional boot up. Make
;the border and screen black. AFTER
;the video memory, etc has finished.
lda #$00
sta $d020
sta $d021
cli
;Switch off the screen.
lda $d011
and #%11101111
sta $d011
;Move transfer code over to the screen
;memory.
ldx #$00
tloop lda transfer,x
sta scr,x
inx
bne tloop
jmp scr
transfer
ldx #$00
tr1 lda linkedgame,x ;Move from linked address
sta $0801,x ;Direct to BASIC start address
inx
bne tr1
inc scr+4
inc scr+7
lda scr+4
bne transfer
jsr $e453 ;load basic vectors
jsr $e3bf ;init basic ram
ldx #$fb
txs
;Execute the game, by jumping to the
;de-cruncher's start address.
;jmp $0820
jmp DecrunchADDR
;Link crunched game as a PRG file to memory after
;the cartridge build code.
linkedgame
!bin "8085sys.prg",,2
FileSize = *
!if FileSize >$c000 {
!error "FILE SIZE IS TOO BIG TO FIT 16KB CARTRIDGE"
} else {
*=$c000
}
Exomizer:
exomizer sfx sys 8085.prg -o 8085sys.prg
Reading "8085.prg", loading from $0801 to $4CE9.
Crunching from $0801 to $4CE9.
Phase 1: Instrumenting file
-----------------------------
Length of indata: 17640 bytes.
[building.directed.acyclic.graph.building.directed.acyclic.graph.]
Instrumenting file, done.
Phase 2: Calculating encoding
-----------------------------
pass 1: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80273.0 bits ~10035 bytes
pass 2: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80039.0 bits ~10005 bytes
pass 3: optimizing ..
Calculating encoding, done.
Phase 3: Generating output file
------------------------------
Encoding: 1101112133423160,1122,2010223445667788,032144406789BBCD
Length of crunched data: 10034 bytes.
Crunched data reduced 7606 bytes (43.12%)
Target is self-decrunching C64 executable,
jmp address $0820.
Writing "8085sys.prg" as prg, saving from $0801 to $304C.
Memory layout: |Start |End |
Crunched data | $07E7| $2F18|
Decrunched data | $0801| $4CE9|
Decrunch table | $0334| $03D0|
Decruncher | $00FD| $01C0| and $9F,$A7,$AE,$AF
Decrunch effect writes to $DBE7.
Decruncher: |Enter |During|Exit |
RAM config | $37| $37| $37|
IRQ enabled | 1| 1| 1|
exomizer sfx $\0801 8085.prg -o 8085out.prg
Reading "8085.prg", loading from $0801 to $4CE9.
Crunching from $0801 to $4CE9.
Phase 1: Instrumenting file
-----------------------------
Length of indata: 17640 bytes.
[building.directed.acyclic.graph.building.directed.acyclic.graph.]
Instrumenting file, done.
Phase 2: Calculating encoding
-----------------------------
pass 1: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80273.0 bits ~10035 bytes
pass 2: optimizing ..
[finding.shortest.path.finding.shortest.path.finding.shortest.pat]
size 80039.0 bits ~10005 bytes
pass 3: optimizing ..
Calculating encoding, done.
Phase 3: Generating output file
------------------------------
Encoding: 1101112133423160,1122,2010223445667788,032144406789BBCD
Length of crunched data: 10034 bytes.
Crunched data reduced 7606 bytes (43.12%)
Target is self-decrunching C64 executable,
jmp address $0801.
Writing "8085out.prg" as prg, saving from $0801 to $304C.
Memory layout: |Start |End |
Crunched data | $07E7| $2F18|
Decrunched data | $0801| $4CE9|
Decrunch table | $0334| $03D0|
Decruncher | $00FD| $01C0| and $9F,$A7,$AE,$AF
Decrunch effect writes to $DBE7.
Decruncher: |Enter |During|Exit |
RAM config | $37| $37| $37|
IRQ enabled | 1| 1| 1|
This looks okay: (monitor in vice)
Attaching crt in vice
Maybe one of these problems:
1) you CAN NOT use BASIC routines when a cart is inserted (without weird tricks, i.e.
storing BASIC routines on cart etc)
2) you need to be careful about $01 as you may map in ROM at $8000 without expecting it.
Please refer to this if in doubt:
http://unusedino.de/ec64/technical/aay/c64/memcfg.html
[3] You should also be careful about the usage of KERNAL routines as some of them
sweep across BASIC-code as well!
After a whole day soldering yesterday, ending up with a wire mess. Which didn’t work at the end…
Starting measuring some things, and create some test sketches (led blinky tests) I found out that the main problem was not having the red switches connected to GND. Blue switches where upside down, this was a easy fix. Because these are ON-ON switches, and where already connected to a common line. Then a mixup between D0 and D6 (wires crossed) And it is working! Made some lines and lettering on the frontplate after some playing around.
Weird to input stuff in octal (group of 3 bits)
"If something is worth doing, it's worth overdoing."
