Tag Archives: hardware

Lilygo PC, 68000 progress and C64 hacks

Made a micro PC using Fabgl library and a ESP32 LilyGo Vga

More info about this device

68000 Progress

My address decoder seems to work (using an ATF22v10C) See previous posts.

Also new Rom and Ram chips. These are 8 bits, but the 68000’s data bus we need two (Odd and Even Addresses)

C64 Hacks

I made a proof of concept for a Rom switcher.
8 Different Roms can be selected using the dip switches.
(Dipswitches are being replaces bij something smarter in the future, like an Arduino Nano (like Adrian Black’s solution)

My other C64 stopped working, I need to make my PLA replacement.
https://www.henriaanstoot.nl/2024/05/27/notes-for-next-projects-i-made-using-our-short-holiday-in-madeira/
But beside the PLA not working, I noticed the glass fuse was blown.
I didn’t have a large fuse (32mm) but a small one.
(Fast 1.6A and 230V)
So some fancy soldering and fixed.

68000 FC signals and Latch demo for Bus Controller

PROCESSOR FUNCTION CODES (FC0, FC1, FC2)
These function code outputs indicate the mode (user or supervisor) and the address space type currently being accessed.

The following table shows the
meaning of these three bits.
FC2 FC1 FC0 Meaning
0 0 0 Not used
0 0 1 User data
0 1 0 User program
0 1 1 Not used
1 0 0 Not used
1 0 1 Supervisor data
1 1 0 Supervisor program
1 1 1 Interrupt Acknowledge
These outputs can therefore inform external circuitry what is happening
inside the 68000. They could, for example, be used to switch in differentbanks of memory.

Using a small 8266 with a display, I wanted to see if it’s useful to monitor this information.

So using a trick with the uln2804/uln2803 as level convertor (don’t connect the VCC, and the output will drop to a level that is around the 3.3v.
(I was out of bi-directional level convertors)


Latch demo

I’ve been using latches in the past, but I wanted to show how it works using a little demo setup.
Below movie is for the Bus Controller I posted recently.

68000 Testing

While busy fixing my business site, and working for a customer, I build a testing rig for the 68000.

I first made a power-on reset schematic.
The timing is different from the 6502 power-on reset, and the 68k needs HALT and RESET being pulled low.

Inverted reset signal (before the 74ls06 invertor)
Schematic with poweron reset, some leds and 8mhz crystal
Lines pulled to GND or VCC are at least needed to get a running CPU.
Data bus resistors are needed because data is r/w

All Data lines are pulled low, emulating opcode 00 00
https://68k.hax.com/ORI%20to%20CCR
This will do nothing weird, and will increment the address and try to read the next opcode.
Resulting in an endless incrementing address bus, I’ve put a Led (Red)on Address A17.

Yellow is /RESET signal and Blue /HALT

Bus Controller / Writer

For my 68000 POC I’ll need a way to test Address and Data buses. Something I also wanted for my 6502.

So I drew a schematic to make a generic bus manipulator.
(Address, Data and some control lines)

Devices I want to control:

  • 6502 – 16 addresses and 8 bit data
  • 6800 – 24 address lines and 16 bits data
  • 808x
  • LCD Displays – 8 bit data – enable, read/write and register select
  • SID Music Chip, AY-3-8910 Music chip

I will be using 8 input switches I can latch into 74HC373 chips.
(3x 8 bit for addresses, or 2x 8 bit and extra control lines + 2x 8 bit datalines)
Using ULN2804A or ULN2803A darlingtons I can use ledbars to display the bus data AND the latched data.
Using 5 pushbuttons I can choose which one (or multiple banks will be latched.
Other 5 buttons shall control the OUTPUT enable (OE), which also can be toggled using 1 master switch.
(Not yet in the schematic)

After testing, I will put the Kicad files online.

68000 ODD EVEN Decoder

First setup to make an address decoder for my 68k

000000 - 007FFF 32k * 16 bits RAM
F80000 - FBFFFF IO0,1,2,3,4
FF0000 - FFFFFF 32k * 16 bits ROM

We need /LDS and /UDS for odd even select, because rom and ram are 8 bits chips.

Also we are not decoding all address lines.

x0xxxx - RAM
F8xxxx - IO
FFxxxx - ROM

This means there are blocks repeated

Address lines
23 22 21 20 19 18 17 16 .....
1  1  1  1  1  1  1  1  * ..... ROM
0  0  0  0  0  0  0  0  * ..... RAM
1  1  1  1  1  0  *  *  * ... IO but A17 A16 are sub selects

Code for ATF22v10
Not used yet! .. not verified!

-------------
GAL22V10
68000addr

Clock   A23   A22   A21   A20    A19   A18    A17    A16    LDS  UDS   GND
/OE   ODDRAM   EVNRAM  ODDROM    EVNROM    IO0    IO1   IO2    IO3   NC   NC VCC


/ODDRAM = /A23 * /A22 * /A21 * /A20 * /A19 * /A18 * /A17 * /A16 * /LDS
/EVNRAM = /A23 * /A22 * /A21 * /A20 * /A19 * /A18 * /A17 * /A16 * /UDS
/ODDROM = A23 * A22 * A21 * A20 * A19 * A18 * A17 * A16 * /LDS
/EVNROM = A23 * A22 * A21 * A20 * A19 * A18 * A17 * A16 * /UDS
/IO0 = A23 * A22 * A21 * A20 * A19 * /A18 * /A17 * /A16 * /LDS
/IO1 = A23 * A22 * A21 * A20 * A19 * /A18 * /A17 * A16 * /LDS
/IO2 = A23 * A22 * A21 * A20 * A19 * /A18 * A17 * /A16 * /LDS
/IO3 = A23 * A22 * A21 * A20 * A19 * /A18 * A17 * A16 * /LDS

DESCRIPTION
A 68000 addr decoder
---------------------------


UPDATE

I’ve got some K6T4008C1B RAM chips now.
These are 512k, but I don’t need that much (for now)
So I’ll still use above decoder and below schematic

68000 SBC, C64 Git and SID Player

Working on 68000 Single Board Computer.

Made a clock circuit and busy designing a power-on-reset schematic. I’ve made one before, but this circuit needs RESET and HALT being pulled low.

8mhz 5V

The 68000 being 24 bit address and 16 bit data needs 2x 8-bit roms and 2x 8 bit ram, but i didn’t have the components yet in this picture.

Address decoder using ATF22V10C is also halfway.
Schematics online soon.

Started a protected Git repo for C64 demo and proof of concepts for our old ICECREW group.

Installed Gitea, behind a reverse proxy.
Part of reverse proxy

ProxyRequests Off
ProxyPreserveHost On
SSLProxyVerify none
SSLProxyCheckPeerCN off
SSLProxyCheckPeerName off

<Location />
ProxyPass   http://10.x.y.z:3000/
ProxyPassReverse  http://10.x.y.z:3000/
Require ip 213.10.144.27
Require ip a.b.c.d
Require ip e.f.g.h
</Location>

Gitea config with token login over https

Generate token
Login https://icecrew.henriaanstoot.nl/

Select your profile (upper right)

And select Settings > Applications

Select a name for your token. And press generate

Top screen shows a token, copy this!

Create new project
Press explore (upper left)

Select organisation and icecrew

Press New Repository, give a name and create

(press https when not defaulted, there is NO ssh to this server)

The example is wrong! (Use below changing TOKENHERE and PROJECTNAME

touch README.md
git init -b master
git add README.md
git commit -m "first commit"
git remote add origin https://TOKENHERE@icecrew.henriaanstoot.nl/icecrew/PROJECTNAME.git
git push -u origin master

Clone a project
Goto a project

press HTTPS when not defaulted to this.

git clone https://icecrew.henriaanstoot.nl/icecrew/borderflag.git 

edit .git/config and add your token to the url ! to push

My Sidplayer as an option to select own collection.
And I’ve made a top list

# Best composers (no order)
Ouwehand_Reyn
Tel_Jeroen
Huelsbeck_Chris
Rowlands_Steve
Hubbard_Rob
Daglish_Ben
Follin_Tim
Gray_Matt
Tjelta_Geir
Mibri (from get in the Van)

# Best tunes (no order)
R-Type.sid
Arkanoid.sid
Bottom.sid
Turbo_Outrun.sid
A_Tune_for_Unity.sid
Ohne_Dich_Rammstein.sid

# Start of own collection (not in above collection)
Abyssus_Ignis_[8580].sid
Catastrophe_[8580].sid
Dumb_Terminal_[8580].sid
Get_in_the_Van_[8580].sid
Getting_in_the_Van_[8580].sid
Supercharger_[8580].sid
Tuna_Guitar_[8580].sid

Investigating syncing effect to Sid music.

I got a great tip from Youth who made the Freakandel demo presented at X2024.

> Setup the loop to play the music

> Copy part of the memory to the screen ($0400) in the same loop to look for memory locations that are used as variables for the music. > Looking at

> Memory where the music is stored

> Zeropage ($00-$ff)

> See if there's some useful changes that coincide with for example drums

> For my own tunes, I use a music routine where I can put event markers in the music itself and react to those from the code. That's >how I synced https://www.micheldebree.nl/posts/big_angry_sprite/

> You could also try reading the SID registers for voice 3 (waveform and ADSR), those are the only ones that are not write-only. > Obviously you can then only react to those changes in voice 3.

I used retrodebugger to see which bytes are changing.
Then I wrote a program which changes the background colour to this value.
I also made a program to use a joystick to see which address have the most interesting effect.
(use up)

     1                                       !to "sidbgnd.prg",cbm
     2                          
     3                                  * = $0801
     4                          			
     5                          sysline:	
     6  0801 0b0801009e323036...        !byte $0b,$08,$01,$00,$9e,$32,$30,$36,$31,$00,$00,$00 ;= SYS 2061
     7                          
     8                                  * = $080d 
     9                          
    10  080d 78                 	sei
    11  080e a960               	lda #<irq
    12  0810 a208               	ldx #>irq
    13  0812 8d1403             	sta $314
    14  0815 8e1503             	stx $315
    15  0818 a91b               	lda #$1b
    16  081a a200               	ldx #$00
    17  081c a07f               	ldy #$7f 
    18  081e 8d11d0             	sta $d011
    19  0821 8e12d0             	stx $d012
    20  0824 8c0ddc             	sty $dc0d
    21  0827 a901               	lda #$01
    22  0829 8d1ad0             	sta $d01a
    23  082c 8d19d0             	sta $d019 
    24  082f a900               	lda #$00
    25  0831 200010             	jsr $1000 
    26  0834 58                 	cli
    27  0835 a920               	lda #$20
    28  0837 8d6b08             	sta vector
    29  083a a917               	lda #$17
    30  083c 8d6c08             	sta vector+1
    31  083f a000               	ldy #$00
    32  0841 b93017             hold 	lda $1730,y
    33  0844 8d20d0             	sta $D020
    34  0847 ad00dc             	lda $dc00
    35  084a 2901               	and #$1
    36  084c c901               	cmp #$1
    37  084e f0f1               	beq hold
    38  0850 ad00dc             	lda $dc00
    39  0853 2901               	and #$1
    40  0855 c900               	cmp #$0
    41  0857 f0e8               	beq hold
    42  0859 c8                 	iny
    43  085a 8c6d08             	sty vector+2
    44  085d 4c4108             	jmp hold 
    45                          irq
    46  0860 a901               	lda #$01
    47  0862 8d19d0             	sta $d019 
    48  0865 200310             	jsr $1003 
    49  0868 4c31ea             	jmp $ea31
    50                          
    51                          vector
    52  086b 0000               	!byte $00,$00
    53                                      
    54                          	* = $1000
    55  1000 4c37104c85104c2f...	!binary "Techno_Drums.sid" ,, $7c+2

Amiga and DIY 68000 single board computer.

Started working on my breadboard version of a 68k computer.
When it’s working, I’ll make a PCB version.
Using almost only parts I still have. (No 8mhz crystal)

The 68000 being 24 bit address and 16 bit data needs 2x 8-bit roms and 2x 8 bit ram, but i didn’t have the components yet in this picture.

While tinkering with above, my Fatter Agnus chip came in.

To make a 1mb chipmem version of your rev 5 amiga (PAL)

You need to have a newer version of the Agnus chip (I had 8371, and bought a 8372a) AND you need a 512kb trapdoor memory expansion.

An unmodded rev 5 will see 512kb Chip mem and 512 Fast mem.

Replacing the Agnus 8371 for 8372a:
I lost my PLCC puller, so I modded a paperclip into a puller 🙂

When placing the new chip, I had to tape pin 41 for PAL version.
I used Polyimide Film tape.

Next I had to cut the jumper 2 connection and solder the other pads.
(Bottom and middle disconnect and middle and top bridged)

Next was another cut on the PCB, this disables the trapdoor card detection.

Success!

Notes for next projects I made using our short holiday in Madeira.

I think we’ve seen Maderia .. 🙂

I bought a little notebook while being there.
I wrote about 12 pages of ideas, schematics and projects to start.

  1. Rewrite Wozmon to use my composite pcb (Atmega328)
    access though via
  2. Building a 68000 pcb with a minimal machine code monitor.
    Using a atf22v10 as address decoder.
    (Same as my 6502 , I love those devices)
    Maybe I’ll add a micro sdcard reader
  3. Add a lcd matrix display to my 8088/8086
  4. Creating a PLA alternative for C64 using ath22v10 (again)
  5. Make backplanes for my 6502, so I can plug cards with different POC cards.
    Clockcard, Latched bus leds, multiple VIA’s, IRQ controller, SID + Buzzer (Maybe also AY-3-8910, see other posts), LCD, composite, serial, Matrix and serial_usb) keyboard)
  6. IRQ controller because I have some devices without opendrain, so I can’t tie all IRQ’s together
  7. Amiga Chip Mem mod for rev 5 (using a ‘new’ 8372A)
  8. 8085 Cartridge new approach
  9. C64Pico fix and add backplane + breadboard version for POCs
  10. … more
First version PLA with atf22v10
PCB mockup (two ATF22v10 on top and a wide pin setup for placement in C64
Wide PLA

8085 Cartridge revisited

Working on 8085 cartridge

Problem with cartridge: prg is 17k, exomized 10k.
So you need 2 banks of 8k.
This disables basic rom, needed for the program.
The program needs to be relocated to 0x800 anyway.
So my exomizer options will take care of that.
But the basic is not being enabled again.

exomizer sfx sys -o data.exo -Di_ram_enter=\$37 -Di_ram_during=\$34 -f'LDA #$37 STA $01' 8085.prg 
xa frame.asm -o frame.bin
x64 -cart16 frame.bin 

Result … JAM